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FPGAs for DSP and Communications

Fee:

$2,635

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Provider:
UCLA Extension

Topic(s):
Technical/Engineering

Who Should Attend?
Engineers

Full Seminar Description

In recent years, the growth of wireless and wireline digital communication has increased exponentially, driven by the continued growth in consumers and the uptake of bandwidth-hungry explosive applications, such as YouTube, Google, and online on-demand TV services. In the last 10 years the migration from low-speed dial-up modem connections of a few kbit/s to DSL broadband speeds of Mbits/s changed the way everybody uses a computer. Up next is another migration, perhaps taking fixed point wireless connectivity of a few Mbits/s using 802.1x standards to the true anytime, anywhere, anyplace mobile wireless connectivity likely to be offered by new technologies such as 3G-LTE. Add to this the continued demand for very high-speed radar, defense systems, and space-based communications, and there is one common element: very high-speed digital signal processing requirements. And best placed to offer flexibility, reprogrammability, and incredible levels of processing power is the FPGA.

In the next few years we can anticipate more communication standards, pervasive computing, and more data available on the move—anytime and anywhere. The requirements for processing speeds on the order of 1,000s of billions of operations per second, rapid prototyping, and software-definable architectures will take FPGAs even further into the DSP communication market. As a snapshot of current technology, some of the latest FPGAs have more than 2,000 multiply/accumulate units on a single device—all capable of being clocked at speeds up to 1GHz. Clearly, therefore, one of the issues is the design requirement for engineers to implement highly parallel, efficient DSP systems.

This intensive short course looks specifically at the use of FPGAs for DSP algorithms, applications, and architectures. Particular emphasis is on communications, given the widespread use of FPGAs in this market and the sheer variety of problems to be solved. The course features both simulation and real design onto FPGA boards provided in the laboratory session of the course. In recent years, project managers, design engineers, software engineers, RF engineers, HDL engineers, and system designers have all taken this course.

Instruction covers:

• The types of DSP problems that may be solved using FPGAs
• A short history of FPGA development and the current "processing" power offered by FPGAs
• FPGA architectures and features
• How to partition and design a DSP algorithm to run efficiently on an FPGA
• Choosing wordlengths and sampling rates
• FPGA implementation metrics (speed, area, power, etc.) and design optimization
• High-speed dedicated arithmetic blocks (DSP48x’s) and their application in DSP designs
• The issues of numerical rounding and truncation, saturation and wraparound, overflow and underflow
• The CORDIC technique: a tool for working with angles and calculating trigonometric functions
• FIR filtering structures for high-speed operation and FPGA architecture support for the FIR
• Retiming and pipelining techniques
• Serial and multichannel filters
• Multirate filtering, including efficient polyphase structures and CIC filters
• Numerical oscillators for digital communications and other applications
• Implementing adaptive filters and other DSP algorithms with feedback
• Adaptive DSP architectures based on the QR algorithm (equalization, beamforming, beamsteering, MIMO)
• The DSP-FPGA design flow and software tools
• FPGA implementation and on-chip verification, with hands-on examples
• Design of digital downconverters (DDCs) and digital upconverters (DUCs)
• Carrier and symbol synchronization on FPGAs
• How to implement advanced communication systems on FPGAs
• Design of control elements for DSP designs

The course is presented in the following format:

• Approximately 60% lectures and FPGA-DSP demonstration
• Approximately 30% hands-on laboratory on FPGA-DSP design/simulation and real hardware design targeting Xilinx devices
• 10% responsive mode to questions, concerns, and requests

This course is designed to complement the highly successful short course, Digital Signal Processing: Theory, Algorithms, and Implementation, presented by UCLA Extension since 1997.

UCLA Extension has presented this highly successful short course since 2003.

Prerequisites

The following experience is useful: computer programming principles and use of an operating system; electrical engineering principles; and bachelor's or master's degree-level mathematics. Some background and awareness of DSP, as well as an awareness of VHDL or Verilog, is useful but not essential.

Course Materials

A comprehensive five-volume set of notes and workbooks, and a copy of a multimedia DVD are distributed on the first day of the course. The DVD is a comprehensive resource for DSP and features the lecture and workbook materials, more than 200 DSP-FPGA examples, and installation information to guide future use of the software used during the course. Access information for evaluation licenses of the software used in the course also is provided. The notes and DVD are for participants only and are not otherwise available for sale or unauthorized distribution.

Laboratory Sessions

Participants work with industry-standard FPGA design tools and learn the complete design flow—from DSP bit-true design and simulation to producing VHDL for synthesis, and to actual FPGA implementation. Xilinx Spartan-6 FPGAs are targeted and all participants take their implementation onto real devices. A UCLA Extension computer laboratory is used to run these sessions.

Daily Schedule

Monday

Introduction to DSP for FPGAs

• Applications and markets of DSP
• DSP before FPGAs!
• From simple gate arrays to high-speed, feature-rich modern devices
• Overview of FPGA layout and elements
• Design creation techniques: system generator
• The design flow from entry to verification
• Principles of DSP for FPGA design
• Critical path, timing and pipelining issues
• The cost of implementing simple arithmetic
• FPGA flexibility: parallel vs. serial implementation
• Case study: design and optimization of a filter bank

FPGA Architectures

• The FPGA array structure, interconnects, and building blocks
• Configurable logic blocks and slice logic
• FPGA memory elements
• Resources for high-speed DSP: DSP48x slices
• Clock generation issues
• FPGA families, series, and their characteristics
• Distributed logic in detail
• Input/output blocks (IOBs) and FPGA packages

DSP Arithmetic Fundamentals

• Unsigned and 2's complement arithmetic
• Fixed-point arithmetic
• Overflow and underflow
• Wraparound and saturation, rounding and truncation
• Fundamental adders and multiplier arrays
• Multiplier implementation alternatives
• FPGA architectural support for high-speed multiply-accumulate
• Division and square root arrays...not so easy!
• Arithmetic wordlength issues
• The CORDIC technique for trigonometric calculations
• Complex arithmetic requirements

Tuesday

FPGA Technology

• FPGA vendors and market position
• Technological milestones in FPGA development
• Comparison of FPGAs with related technologies
• Resource and performance comparison of current FPGAs
• DSP48x resources in detail
• Static and dynamic power consumption
• The “Platform FPGA” concept
• Communications interfaces
• Advanced techniques: embedded processors and partial reconfiguration

Numerically Controlled Oscillators (NCOs)

• Motivation for generating sine and cosine waves
• Lookup table (LUT)-based NCOs
• NCO design parameters with numerical examples
• Frequency resolution
• Spurious free dynamic range (SFDR) as a measure of NCO output quality
• Dithering
• CORDIC-based oscillators
• Simple, low-cost IIR-based oscillators

Linear Systems DSP Algorithm Review

• Sampling and quantization
• Z-domain notation and fundamental analysis
• Frequency domain analysis
• Finite Impulse Response (FIR) digital filters
• Infinite Impulse Response (IIR) digital filters
• Digital filter design and specification techniques

Digital Filtering for FPGAs

• Filter designs and implementation parameters
• Efficient arithmetic for FIR filters
• Simple filters: the moving average and integrator-comb
• Symmetric/linear phase filters
• Serial filter implementations: sharing the MAC unit
• Filter throughput and cost trade-off
• Multichannel architectures
• Distributed filter implementations: low-cost shift-and-add techniques

Wednesday

Signal Flow Graph (SFG) Techniques

• DSP/digital filter signal flow graphs
• Latency, delays, and "anti-delays"
• Re-timing: cut-set techniques
• The transpose and systolic forms of the FIR
• DSP48x support for common FIR filter structures
• Exploiting filter symmetry using a pre-adder
• Delay scaling and multichannel implementations
• Old ideas—new enthusiasm: systolic arrays

Multirate Digital Filtering

• Motivations for changing the sampling rate
• The processes of interpolation and decimation
• Designing anti-alias and anti-image filters
• The Noble Identity
• Efficient “polyphase” filter implementations
• Strategic filter responses: half-band and L-band filters
• Cascade Integrator Comb (CIC) Filters (Hogenauer)
• Design tool support for single-rate and multirate filters

Adaptive DSP Algorithms and Applications

• Motivation for adaptive filters and classes of problem
• The Weiner-Hopf solution
• The LMS algorithm and variations
• LMS signal flow graph and application of pipelining techniques
• Non-canonical LMS algorithms for FPGA
• Channel equalization
• (Bandpass) complex arithmetic requirements
• The need for speed!—LMS vs. RLS algorithms

Thursday

Adaptive QR Algorithm Techniques

• Adaptive problems in wireless communications
• Classic least squares problems
• Linear algebra and matrix review
• Fixed-point, dynamic range, and other arithmetic issues
• The QR Algorithm for matrix "inversion"
• Givens rotations for QR implementation
• CORDIC for QR calculations
• The QR triangular array
• Backsubstitution and downdating methods
• Adaptive equalization and beamforming

DSP-Enabled Communications Using FPGAs

• Quatenary Phase Shift Keying (QPSK) and variants
• Root raised cosine pulse shaping, transmit and receive filters
• Digital up- and downconverter (DUC and DDC) architectures
• Filter chains for transmit and receive sampling rate transitions
• DUC and DDC design examples
• Undersampling and direct digital downconversion
• Digital IF stages (and fs/4 systems)

Synchronization Issues in Communications

• The need for synchronization
• The phase locked loop (PLL) and design parameters
• Carrier synchronization: squaring loops and Costas loops
• Phase rotations
• Symbol timing recovery and maximum effect points
• Early/late gate detection

Control Elements for DSP

• Counters and multiplexers
• Finite state machines
• “Black boxes”—incorporating VHDL/Verilog code
• Mcode—control with MATLAB-type commands
• Embedded processors
• Design for DSP "System-on-Chip"

Design, Simulation, and Implementation Case Studies

• Introduction to the design flow and software tools
• FPGA hardware examples and real-time on-FPGA debugging with ChipScope
• Building delay lines and shift registers
• Inspection of low-level implementation details: adder case study
• Clock specification and synthesis techniques
• Numerically controlled oscillator designs using LUT and CORDIC methods
• Sine wave synthesis: hands-on/listening examples
• CORDIC vector magnitude and trigonometric calculations
• Audio filtering case study
• Hardware co-simulation on the FPGA development board
• DSP48x-based filter designs
• High-speed FFT implementation
• High-speed CIC filter design
• Digital up- and downconverter designs
• QR system identification examples
• Timing and synchronization circuits
• Leveraging Xilinx compilers for rapid design creation

Sponsor Background:

The courses range from two-to-five days in length and attract participants from across the United States and Internationally. Subject areas include electrical, materials, and mechanical engineering as well as computer and communications engineering and technical management. Nearly 100 courses per year are held on the UCLA campus in Los Angeles. Many of them are also presented under contract at company locations across the country and abroad.

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