FPGAs for DSP and Communications

Complete Seminar Details

In just the last five years, the growth of wireless and wireline digital communication has increased exponentially. On a consumer level, this is evident from the rapid uptake of DSL broadband-type services for home Web access and the now widespread use of wireless LANs and mobile interconnects. The use of DSP cores, processors, and ASICs is fundamental to the implementation of the algorithms and architectures for these applications. In the last few years, however, we have noted that the cost gap between DSP cores/processors and full custom ASIC is being traversed by a new powerful generation of FPGAs (Field Programmable Gate Arrays).

In the next five years we can anticipate more communication standards, more pervasive computing, and more data available on the move--anytime and anywhere. The requirements for processing speeds on the order of tens or hundreds of billions of operations per second, rapid prototyping, and software-definable architectures will further the penetration of FPGAs into the DSP communication market. Traditionally we have found FPGAs providing an integrated device for sequential and combinational logic operations in many applications; however, more recently the increased flexibility, programmability, and capability of FPGAs for fast and customized multiply-accumulate has meant that in many DSP applications they are the first choice for hardware verification, rapid prototyping, and--in many cases--final product and system design.

In this intensive course, the use of FPGAs is looked at specifically for DSP algorithms, applications, and architectures. Particular emphasis is on communications given the widespread use of FPGAs in this market and the sheer variety of problems to be solved. The course features both simulation and real design onto FPGA DSP boards provided in the laboratory section of the course.

Instruction covers:

• When to use an FPGA rather than a DSP processor or core
• The current "processing" power offered by FPGAs and different vendors
• How to efficiently implement DSP algorithms on FPGAs
• The issues and new design paradigms concerning wordlength and high sampling rates
• The different ways to structure the arithmetic required for DSP
• The issues of numerical rounding and truncation, saturation and wraparound, overflow and underflow
• Techniques to simplify the arithmetic (oversampling, CIC filters, etc.)
• How to partition and design a DSP algorithm to run efficiently on an FPGA
• Working with feedback DSP algorithms and architectures
• How to implement advanced communication systems on FPGAs
• The strategy of using FPGA and DSP design software
• Full design, simulate, and FPGA implementations of adaptive systems and downconverters
• Working with embedded processors on FPGAs
• Digital communications synchronization on FPGAs

The course is presented in the following format:

• Approximately 60 percent lectures and FPGA-DSP demonstration
• Approximately 30 percent hands-on laboratory on FPGA-DSP
design/simulation and real hardware design using the Xilinx Virtex II Pro device
• 10 percent responsive mode to questions, concerns, and requests
• This course is designed to complement the highly successful short course, Digital Signal Processing: Theory, Algorithms, and Implementation, presented by UCLA Extension since 1997.

UCLA Extension has presented this highly successful short course since 2003.

Prerequisites

The following experience is useful: computer programming principles and use of an operating system; electrical engineering principles; and bachelor's or master's degree-level mathematics. Some background and awareness of DSP is useful although not essential. An awareness of VHDL or Verilog is useful but not essential to this course.

Course Materials

A comprehensive four-volume set of notes and a copy of a multimedia CD is distributed on the first day of the course. The CD is a comprehensive resource for DSP and features the materials and access to evaluation licenses for the software used in the course for DSP-FPGA system design and implementation. The notes and CD are for participants only and are not for sale.

Laboratory Sessions

Participants work with industry-standard FPGA design tools and learn the complete design flow, from DSP bit-true design and simulation design to producing VHDL for synthesis to actual FPGA implementation. Xilinx Virtex II Pro FPGAs are targeted and all participants take their implementation onto real devices. A UCLA Extension computer laboratory is used to run these sessions.

Daily Schedule

Monday

Introduction to DSP Hardware Technologies

• From discrete logic to FPGAs
• The generic DSP system
• DSP cores and processors review
• Custom and semi-custom ASICs
• System-on-chip (SOC)
• FPGA flexibility and functionality
• FPGAs vs. programmable DSPs
• How fast is fast?

Linear Systems DSP Algorithm Review

• Aliasing and reconstruction filters
• Sampling rates and wordlengths
• Z-domain notation and fundamental analysis
• Frequency domain analysis
• Finite Impulse Response (FIR) digital filters
• Infinite Impulse Response (IIR) digital filters
• Digital filter design and specification techniques
• Oversampling techniques
• Sigma Delta strategies

FPGA Technology

• The FPGA technology roadmap
• Clocking rates, data rates, and sample rates
• FPGA memory and registers
• Input/output blocks and requirements
• Programmable interconnects
• FPGA vendors/manufacturers
• Bits, slices, and configurable logic blocks
• Comparable MIPs performance ratings
• FPGA families and sources
• Review of essential VHDL

DSP Arithmetic Fundamentals

• 2's complement fixed-point arithmetic
• Fundamental adders and multiplier arrays
• Division and square root arrays...not so easy
• Wordlength issues
• Fixed-point arithmetic
• Overflow and underflow
• CORDIC techniques
• Complex arithmetic requirements

Tuesday

FPGA Elements for DSP Algorithms

• Building delay lines and shift registers
• Use of RAM (memory) on FPGAs
• Serial to parallel and parallel to serial
• Multiplexors for channel selection
• Full adders, carry logic, and adder trees
• Multipliers: shift and add; ROM-based
• (K)Constant Coefficient Multiplier (KCM)
• Minimum size multipliers
• Dedicated on-chip "hardware" multipliers

Signal Flow Graph (SFG) Techniques

• DSP/digital filter signal flow graphs
• Latency, delays, and "anti-delays"
• Re-timing: cut-set techniques
• Delay scaling and multichannel implementations
• The transpose FIR
• Pipelining and multichannel architectures
• Old ideas--new enthusiasm: systolic arrays
• SFG topologies for FPGAs

"Strategic" Digital Filtering for FPGAs

• Symmetric/linear phase filters
• Upsampling and interpolation filters
• Downsampling and decimation filters
• 1-bit oversampled (sigma-delta) data streams
• Efficient arithmetic for FIR implementation
• Integrators and differentiators
• Half-band, moving average, and comb filters
• Cascade Integrator Comb (CIC) Filters (Hogenauer)
• Efficient arithmetic for IIR filtering

Adaptive DSP Algorithms and Applications

• LMS algorithms
• FPGA pipelining techniques
• Non-canonical LMS algorithms for FPGA
• Feedforward (linear) equalizers
• Decision feedback equalizers (DFE)
• (Bandpass) complex arithmetic requirements
• Synchronization and fractionally space equalizers

Wednesday

DSP-Enabled Communications Using FPGAs

• Quatenary Phase Shift Keying (QPSK) and variants
• Transmit/receive filters--root-raised cosine
• Undersampling and direct digital downconversion
• Direct digital upconversion
• Digital IF stages (and fs/4 systems)
• Spread spectrum
• Design partitioning for Xilinx FPGA

Timing, Synchronization Issues

• Carrier recovery
• Squaring loops, Costas loops, PLLs
• Phase rotations
• Sampling rate conversions
• Symbol timing recovery, early/late gate detection
• Multirate and polyphase filters
• Numerically controlled oscillators

Channel Coding and Decoding

• Channel coding on FPGAs--the easy stuff
• Convolutional and turbo coding
• Block and Reed Solomon coding
• Channel decoding on FPGAs--the not-so-easy stuff

Thursday

Embedded Processors and the DSP "System-on-Chip"

• Embedded processors and controlling the datapath
• The Xilinx Picoblaze Microcontroller
• The Xilinx Microblaze Microcontroller
• Digital filtering using the Microblaze
• PowerPC embedded processors
• Design for DSP "System-on-Chip"

Case Studies Design, Simulation, and Implementation

• Efficient VHDL digital FIR filter design
• Design of optimized 3G transmit root raised cosine filters
• Adaptive LMS equalizer at fs = 10MHz
• Numerically controlled oscillator design
• High-speed FFT implementation
• High-speed CIC filter design
• 80MHz IF Direct Digital Downconverter (DDC)
• Complex multiplier phase rotator
• Adaptive DSP using QR linear algebra techniques
• Timing and synchronization circuits
• Spread spectrum: chipping and channelization implementation

Sponsor Background:

The courses range from two-to-five days in length and attract participants from across the United States and Internationally. Subject areas include electrical, materials, and mechanical engineering as well as computer and communications engineering and technical management. Nearly 100 courses per year are held on the UCLA campus in Los Angeles. Many of them are also presented under contract at company locations across the country and abroad.